id4_common.devices.softgluezynq_g#
SoftGlueZynq
Module Contents#
- id4_common.devices.softgluezynq_g.logger#
- class id4_common.devices.softgluezynq_g.SoftGlueZynqDevice(*args, reset_sleep_time=0.2, reference_clock=10000000.0, **kwargs)#
Bases:
ophyd.DeviceSoftGlue Zynq FPGA timing device for 4IDG flyscans (counters, DMA, I/O).
- preset_monitor#
- dma#
- buffers#
- io#
- up_counter_count#
- up_counter_trigger#
- up_counter_gate_on#
- up_counter_gate_off#
- div_by_n_count#
- div_by_n_trigger#
- div_by_n_interrupt#
- gate_trigger#
- scaltostream#
- clocks#
- clock_freq#
- sample_pos#
- start_softglue()#
Bluesky plan stub to assert the global enable buffer (in1 = ‘1’).
- stop_softglue()#
Bluesky plan stub to de-assert the global enable buffer (in1 = ‘0’).
- start_detectors()#
Bluesky plan stub to assert the detector enable buffer (in2 = ‘1’).
- stop_detectors()#
Bluesky plan stub to de-assert the detector enable buffer (in2 = ‘0’).
- reset_plan()#
Bluesky plan stub to pulse the counter-reset and DMA-reset buffers.
- clear_enable_dma()#
Bluesky plan stub to clear the DMA buffer and then enable DMA acquisition.
- clear_disable_dma()#
Bluesky plan stub to clear the DMA buffer and then disable DMA acquisition.
- setup_trigger_plan(period_time, pulse_width_time, pulse_delay_time=0)#
Bluesky plan stub to configure the trigger period, pulse width, and delay in clock ticks.
- setup_count_plan(time)#
Bluesky plan stub to set the count divider N for the given count time in seconds.
- default_settings(timeout=10)#
Apply default FPGA settings (no-op for this class; subclasses override).